vProto - utilizes a human-perceptible State Machine and generates C++ code based on it to facilitate state transitions when parsing incoming data. It's extremely convenient for parsing existing protocols as well as describing custom ones. It's designed to work with any data fragmentation (data can arrive even byte by byte), which is highly relevant for the TCP protocol.
vSyn - transfer (translator) C language to Verilog. The development of algorithms in the C language is significantly simpler, more compact, and faster than in hardware description languages (Verilog, VHDL, SystemC, etc).
An automated process of transferring C logic to the hardware level is a highly effective approach in implementing complex and large projects on PLDs (Programmable Logic Devices) FPGA:
These devices were 100% developed by me, including schematic design in Altium Designer, PCB layout, manual soldering of prototypes, and programming of both FPGA and microcontrollers. The development took place at home, outside of working hours, but later some of these devices were sold and went into mass production